Rambus & Kingston Develop Threaded Module Prototype

Rambus Inc. ,
one of the world’s premier technology licensing companies specializing
in high-speed memory architectures, and Kingston Technology, the
independent world leader in memory products, today announced a
collaborative development of a threaded module prototype using DDR3
DRAM technology. Initial silicon results show an improvement in data
throughput of up to 50 percent, while reducing power consumption by 20
percent compared to conventional modules.

As demand grows for throughput-intensive computing in notebooks,
desktops and servers, the performance requirements on DRAM memory
subsystems rises dramatically. As a result, multi-core computing
requires more bandwidth and higher rates of random access from DRAM

“As multi-core computing becomes pervasive, DRAM memory subsystems
will be severely challenged to deliver the data throughput required,”
said Craig Hampel, Rambus Fellow. “Our innovative module threading
technology employs parallelism to deliver the higher memory bandwidth
needed for multi-core systems while reducing overall power consumption.”

“Kingston is at the forefront of memory technology working closely
with innovators like Rambus to develop advanced solutions,” said Dr.
Ramon Co, vice president of Worldwide Test Engineering at Kingston
Technology. “The collaboration of our experienced teams produced a
memory solution that helps overcome a major challenge with multi-core

Threaded memory module technology is implemented utilizing
industry-standard DDR3 devices and a conventional module
infrastructure. It is capable of providing greater power efficiency for
computing systems by partitioning modules into multiple independent
channels that share a common command/address port. Threaded modules can
support 64-byte memory transfers at full bus utilization, resulting in
efficiency gains of up to 50 percent when compared to current DDR3
memory modules. In addition, DRAMs in threaded modules are activated
half as often as in conventional modules, resulting in a 20 percent
reduction in overall module power.

Rambus will showcase a static demonstration of this prototype at the
Intel Developer Forum, September 22 – 24, 2009 at Moscone West in San
Francisco, CA. In addition, Rambus Fellow Craig Hampel will discuss the
benefits of threaded modules in multi-core computing applications
during a talk at the Intel Developer Forum, September 22, 2009, at
11:15 a.m.


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