Cypress Introduces Industry First 65-nm 144-Mbit SRAMs

Cypress Semiconductor Corp., an industry leader in SRAMs, today announced the industry’s first monolithic SRAMs at 144-Mbit densities, the latest members of its 65-nm SRAM family. The new 144-Mbit QDRII, QDRII+, DDRII and DDRII+ memories leverage 65-nm process technology developed with foundry partner UMC. They feature the market’s fastest available clock speed of 550 MHz and a total data rate of 80 Gbps in a 36-bit I/O width QDRII+ device, and consume half the power of 90-nm SRAMs. They are ideal for networking applications, including Internet core and edge routers, fixed and modular Ethernet switches, 3G base stations and secure routers, and also enhance the performance of medical imaging and military signal processing systems. The devices are pin compatible with 90-nm SRAMs, enabling networking customers to increase performance and double address table or packet buffer size while maintaining the same board layout.

Compared with 90-nm SRAMs, Cypress’s 65-nm QDR and DDR SRAMs offer up to 50% lower standby and dynamic current consumption, enabling the new wave of “green” networking infrastructure applications. The QDRII+ and DDRII+ devices have On-Die Termination (ODT), which improves signal integrity, reduces system cost, and saves board space by eliminating external termination resistors. The 65-nm devices use a Phase Locked Loop (PLL) instead of a Delay Locked Loop (DLL), which enables a 35 percent wider data valid window to simplify board-level timing closure and enhance compatibility with third-party processors.

“As the worldwide leader in SRAMs, we offer by far the industry’s broadest portfolio,” said Dave Kranzler, Vice President of Sync and Timing Products at Cypress. “This introduction widens our lead by providing the fastest, largest devices in the industry. It’s another clear indication of our commitment to the SRAM market.”

Availability and Photo

The CY7C16xxKV18 65-nm QDRII, QDRII+, DDRII and DDRII+ SRAMs are all currently sampling, with production expected in Q1 2010. Each device is available in multiple configurations based on I/O width (x18 or x36), burst length (B4 or B2) and latency (1.5, 2.0 or 2.5). The 65-nm 144-Mbit SRAMs are available in industry-standard 165 FBGA packages and are pin-compatible with existing 90-nm QDR and DDR devices for easy migration. A high-resolution photo of the QDRII+ SRAM is available at


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