Intel Corporation showcased a wafer with dual-core Intel Itanium 2 “Montecito” dies at an event in Japan recently. The demonstration reiterates Intel’s commitment to the IA64 architecture and indicates that the company is on-track to mass produce dual-core 64-bit chips next year.
Dual-Core, DDR2, PCI Express Ahead
Montecito will be Intel’s first IA64 chip with two cores and 24MB of L3 cache. In 2003 Intel uncovered plans to implement its special “arbiter” bus into the chip code-named Montecito to manage how the cores collaborate between themselves, how they utilise their processor system bus and the L3 cache. No actual peculiarities of the design have been presented by Intel officials so far, but we can pre-suppose that the “arbiter” bus architecture may be utilised in all multiple-core CPUs from Intel that will come in future. Millington is a cheaper version of Montecito, probably tailored to serve 2P systems and contain less cache, LV Millington will have lower power consumption compared to the default core.
The Montecito and Millington chips will contain a couple of promising technologies: Foxton for dynamic power management and Pellston for correcting data errors in the cache. Intel’s president and COO Paul Otellini recently said that the Foxton is a technology to dynamically boost speed of Itanium 2 chips, but he did not outline, whether this applies to dynamic overclocking or dynamic underclocking. Typically, overclocking is not accepted in mission-critical environments, at the same time, dynamic underclocking can help to reduce power consumption and consequently the cost of ownership.
Intel’s Itanium 2 chips with two processing engine will work using 667MHz Quad Pumped Bus and will feature Intel’s new core-logic for high-end servers code-named Bayshore. The latter is expected to provide support for DDR2 memory and PCI Express interconnection, bringing the latest innovations into the server market.
News source: Xbit Labs
