Rambus to Demonstrate High-Performance, Low-Power Memory Technologies

Join Rambus at Mobile World Congress 2009 for a silicon test demonstration of its recently announced Mobile Memory Initiative. This development effort focuses on high-bandwidth, low-power memory technologies targeted at achieving data rates of 4.3Gbps at best-in-class power efficiency. With this performance, designers could realize more than 17GB/s of memory bandwidth from a single mobile DRAM device.

Rambus has combined its high-bandwidth expertise with power-efficient signaling technology to create key innovations for its Mobile Memory Initiative, such as:

1.Very Low-Swing Differential Signaling — combines the robust signaling qualities of a differential architecture with innovative circuit techniques to greatly reduce active power consumption;

2.FlexClocking Architecture — a clock-forwarded and clock-distributed topology, enables high-speed operation and a simplified DRAM interface; and

3.Advanced Power State Management — in conjunction with the FlexClocking architecture, provides fast switching times between power-saving modes and delivers optimized power efficiency across a diverse range of usage profiles. Who:
Rambus Inc.

Mobile World Congress
Booth #7A57
Fira de Barcelona
Barcelona, Spain

February 16-19, 2009


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