Join Rambus at Mobile World Congress 2009 for a silicon test demonstration of its recently announced Mobile Memory Initiative. This development effort focuses on high-bandwidth, low-power memory technologies targeted at achieving data rates of 4.3Gbps at best-in-class power efficiency. With this performance, designers could realize more than 17GB/s of memory bandwidth from a single mobile DRAM device.
Rambus has combined its high-bandwidth expertise with power-efficient signaling technology to create key innovations for its Mobile Memory Initiative, such as:
1.Very Low-Swing Differential Signaling â€” combines the robust signaling qualities of a differential architecture with innovative circuit techniques to greatly reduce active power consumption;
2.FlexClocking Architecture â€” a clock-forwarded and clock-distributed topology, enables high-speed operation and a simplified DRAM interface; and
3.Advanced Power State Management â€” in conjunction with the FlexClocking architecture, provides fast switching times between power-saving modes and delivers optimized power efficiency across a diverse range of usage profiles. Who:
Mobile World Congress
Fira de Barcelona
February 16-19, 2009