MoSys Announces 40nm DDR3 and DDR3/2 Combo PHYs

MoSys, Inc., a leading supplier of high-density embedded memory and high-datarate parallel and serial interface IP, today announced the availability of its silicon-proven DDR3 and DDR3/2 combo PHYs. MoSys’ fully-integrated solution complies with the latest DFI specification and provides the physical layer (PHY) interface between the controller logic and DDR3/2 DRAM devices. The DDR3/2 PHYs can achieve datarates up to 1600Mbps in a wirebond package and 2133Mbps in flip chip packaging, making them well-suited for both high -performance and cost-sensitive designs.

“Our high-performance memory controllers and predictable protocol verification portfolio are the industry’s most widely used, silicon-proven solutions,” said David Lin, Vice President of Marketing at Denali Software, Inc. “MoSys’ DDR3/2 Combo PHY extends our ability to provide best-in-class, end-to-end memory interconnect solutions to our mutual customers.”

“DDR3 is rapidly gaining adoption as the next generation of the DDR memory interface,” said David DeMaria, Vice President of Business Operations at MoSys. "The availability of our DDR3/2 Combo PHY and its seamless interoperability with Denali’s Memory Controller ensures speedy time-to-market for our customers’ chip designs."

"The high speed interface requirements for our ASICs are demanding," said Anil Mankar, Senior Vice President of VLSI Engineering for Mindspeed Technologies. “We selected the DDR3 solution from MoSys because it precisely met our requirements."

MoSys’ DFI 2.1 compliant DDR 3/2 PHY product is available to chip designers using 40nm and 65nm processes. MoSys’s DDR 3/2 Combo PHY solution is available in both wirebond and flipchip configurations. Offering a choice of 1.8V or 2.5V IO FETs, the DDR PHYs support datarates up to 2133Mbps.


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